OETC Receiver Array

This chip was designed for the OptoElectronics Technology Consortium which was a collaboration between  IBM Research, AT&T, Honeywell, and Martin Marietta to develop key opto-electronic components that advance interconnect technology beyond current cost, speed, and density barriers. I was the project leader for this receiver at IBM and designed the low noise front end. The chip is a 32 channel fiber optic receiver array using integrated MSM detectors and GaAs MesFET technology. Each channel contained a transimpedence preamplifier, level restore circuit, post amplifier, 50 ohm drive and operated at 500 Mb/s for an agregate data rate of 2 Gbytes/sec. We suceeded in fabricating and testing the array with very high yield. At the time this was the largest OEIC fabricated to date.

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